1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3dg7267v-d2 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary* january 2005 rev. 1 512mb C 2x32mx72, sdram unbuffered description the w3dg7267v is organized as a 2x32mx72 synchronous dram mod ule which consists of eighteen 32mx8 sdram com po nents in tsop ii package, and one 2k eeprom in an 8 pin tssop package for serial presence detect which are mount ed on a 168 pin dimm mul ti lay er fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change without notice. note: consult factory for availability of: ? lead-free products ? vendor source control options ? industrial temperature options features burst mode operation auto and self refresh capability lvttl compatible inputs and outputs serial presence detect with eeprom fully synchronous: all signals are registered on the positive edge of the system clock programmable burst lengths: 1, 2, 4, 8 or full page power supply: 3.3v 0.3v jedec standard 168 pin dimm package pin names a0 C a12 address input (multiplexed) ba0-1 select bank dq0-63 data input/output cb0-cb7 check bit (data-in/data-out) ck0-ck3 clock input cke0, cke1 clock enable input cs0#,cs3# chip select input ras# row address strobe cas# column address strobe we# write enable dqm0-7 dqm v cc power supply (3.3v) v ss ground *v ref power supply for reference sda serial data i/o scl serial clock sa0-2 address in eeprom dnu do not use nc no connect * these pins are not used in this module. ** these pins should be nc in the system which does not support spd. pin configurations (front side/back side) pin front pin front pin front pin back pin back pin back 1v ss 29 dqm1 57 dq18 85 v ss 113 dqm5 141 dq50 2 dq0 30 cs0# 58 dq19 86 dq32 114 cs1# 142 dq51 3 dq1 31 dnu 59 v cc 87 dq33 115 ras# 143 v cc 4 dq2 32 v ss 60 dq20 88 dq34 116 v ss 144 dq52 5 dq3 33 a0 61 nc 89 dq35 117 a1 145 nc 6v cc 34 a2 62 *v ref 90 v cc 118 a3 146 *v ref 7 dq4 35 a4 63 *cke1 91 dq36 119 a5 147 nc 8 dq5 36 a6 64 v ss 92 dq37 120 a7 148 v ss 9 dq6 37 a8 65 dq21 93 dq38 121 a9 149 dq53 10 dq7 38 a10/ap 66 dq22 94 dq39 122 ba0 150 dq54 11 dq8 39 ba1 67 dq23 95 dq40 123 a11 151 dq55 12 v ss 40 v cc 68 v ss 96 v ss 124 v cc 152 v ss 13 dq9 41 v cc 69 dq24 97 dq41 125 ck1 153 dq56 14 dq10 42 ck0 70 dq25 98 dq42 126 a12 154 dq57 15 dq11 43 v ss 71 dq26 99 dq43 127 v ss 155 dq58 16 dq12 44 dnu 72 dq27 100 dq44 128 cke0 156 dq59 17 dq13 45 cs2# 73 v cc 101 dq45 129 cs3# 157 v cc 18 v cc 46 dqm2 74 dq28 102 v cc 130 dqm6 158 dq60 19 dq14 47 dqm3 75 dq29 103 dq46 131 dqm7 159 dq61 20 dq15 48 dnu 76 dq30 104 dq47 132 *a13 160 dq62 21 cb0 49 v cc 77 dq31 105 cb4 133 v cc 161 dq63 22 cb1 50 nc 78 v ss 106 cb5 134 nc 162 v ss 23 vss 51 nc 79 ck2 107 v ss 135 nc 163 ck3 24 nc 52 cb2 80 nc 108 nc 136 cb6 164 nc 25 nc 53 cb3 81 nc 109 nc 137 cb7 165 **sa0 26 v cc 54 v ss 82 **sda 110 v cc 138 v ss 166 **sa1 27 we# 55 dq16 83 **scl 111 cas# 139 dq48 167 **sa2 28 dqm0 56 dq17 84 v cc 112 dqm4 140 dq49 168 v cc
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3dg7267v-d2 january 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary functional block diagram v cc v ss one 0.1uf and one 0.22 uf cap. per each sdram to all sdrams 10w dqn every dqpin of sdram sda scl a1 a2 a0 sa1 sa2 sa0 wp 47kw cke1 sdram dqm1 dqm5 dqm3 dqm2 cs2# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqm cs# dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dqm cs# dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqm cs# dqm0 cs0# dqm4 dqm6 dqm7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 1 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# cs1# cs3# serial pd dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqm cs# a0-a12, ba0 & 1 cke0 ras# cas# we# sdram sdram sdram sdram sdram v cc
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3dg7267v-d2 january 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v cc supply relative to v ss v cc , v ccq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 18 w short circuit current i os 50 ma note: permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. recommended dc operating conditions voltage referenced to: v ss = 0v, 0c t a 70 parameter symbol min typ max unit note supply voltage v cc 3.0 3.3 3.6 v input high voltage v ih 2.0 3.0 v ccq +0.3 v 1 input low voltage v il -0.3 0.8 v 2 output high voltage v oh 2.4 v i oh = -2ma output low voltage v ol 0.4vi ol = -2ma input leakage current i li -10 10 a 3 note: 1. v ih (max)= 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min)= -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ccq input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. capacitance t a = 25 c, f = 1mhz, v cc = 3.3v, v ref = 1.4v 200mv parameter symbol max unit input capacitance (a0-a12) c in1 74 pf input capacitance (ras#,cas#,we#) c in2 74 pf input capacitance (cke0) c in3 74 pf input capacitance (clk0) c in4 16 pf input capacitance (cs0#,cs2#) c in5 24 pf input capacitance (dqm0-dqm7) c in6 15 pf input capacitance (ba0-ba1) c in7 74 pf data input/output capacitance (dq0-dq63) c out 15 pf data input/output capacitance (cb0-cb7) c out1 15 pf
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3dg7267v-d2 january 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary operating current characteristics v cc = 3.3v, 0c t a 70c parameters symbol conditions versions units note 133/100 operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i ol = 0ma 1620 ma 1 precharge standby current in power down mode i cc2p c ke v il (max), t cc = 10ns 36 ma i cc2ps c ke & clk v il (max), t cc = 36 ma precharge standby current in non-power down mode i cc2n c ke v ih (min), cs v ih (min), t cc =10ns input signals are charged one time during 20 360 ma i cc2ns c ke v ih (min), clk v il (max), t cc = input signals are stable 180 ma active standby current in power-down mode i cc3p c ke v il (max), t cc = 10ns 108 ma i cc3ps c ke & clk v il (max), t cc = 108 active standby in current non power- down mode i cc3n c ke v ih (min), cs v ih (min), t cc = 10ns input signals are charged one time during 20ns 450 ma i cc3ns c ke v ih (min), clk v il (max), t cc = input signals are stable 450 ma operating current (burst mode) i cc4 io = ma page burst 4 banks activated t ccd = 2clk 2340 ma 1 refresh current i cc5 t rc t rc (min) 3240 ma 2 self refresh current i cc6 c ke 0.2v 54 ma notes: 1. measured with outputs open. 2. refresh period is 64ms.
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3dg7267v-d2 january 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary electrical characteristics and recommended ac operating conditions v cc , v ccq = +3.3v 0.3v ac characteristics symbol 7 7.5 10 units note parameter min max min max min max access timefrom clk (pos.edge) cl = 3 t ac(3) 5.4 5.4 6 ns 27 cl = 2 t ac(2) 5.4 6 6 ns address hold time t ah 0.8 0.8 1 ns address setup time t as 1.5 1.5 2 ns clk high-level width t ch 2.5 2.5 3 ns clk low-level width t cl 2.5 2.5 3 ns clock cycle time cl = 3 t ck(3) 7 7.5 8 ns 23 cl = 2 t ck(2) 7.5 10 10 ns 23 cke hold time t ckh 0.8 0.8 1 ns cke setup time t cks 1.5 1.5 2 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 0.8 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 2 ns data-in hold time t dh 0.8 0.8 1 ns data-in setup time t ds 1.5 1.5 2 ns data-out high-impedance time cl = 3 t hz(3) 5.4 5.4 6 ns 10 cl = 2 t hz(2) 5.4 6 6 ns 10 data-out low-impedance time t lz 111ns data-out hold time (load) t oh 2.7 2.7 2.7 ns data-out hold time (no load) t ohn 1.8 1.8 1.8 ns 28 active to precharge command t ras 37 120,000 44 120,000 50 120,000 ns active to active command period t rc 60 66 66 ns active to read or write delay t rcd 15 20 20 ns refresh period t ref 64 64 64 ms autorefresh period t rfc 66 66 66 ns precharge command period t rp 15 20 20 ns active bank a to active bank b command t rrd 14 15 15 ns transition time t t 0.3 1.2 0.3 1.2 0.3 1.2 ns 7 write recovery time t wr 1 clk + 7ns 1 clk + 7.5ns 1 clk + 7.5ns 24 14 15 15 ns 25 exit self refresh to active command t xsr 67 75 80 ns 20
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3dg7267v-d2 january 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary ac functional characteristics v cc , v ccq = +3.3v 0.3v parameter symbol 7 7.5 10 units notes read/write command to read/write command t ccd 111t ck 17 cke to clock disable or power-down entry mode t cked 111t ck 14 cke to clock enable or power-down exit setup mode t ped 111t ck 14 dqm to input data delay t dqd 000t ck 17 dqm to data mask during writes t dqm 000t ck 17 dqmto data high-impedance during reads t dqz 222t ck 17 write command to input data delay t dwd 000t ck 17 data-into active command t dal 455t ck 15, 21 data-into precharge command t dpl 222t ck 16, 21 last data-in to burst stop command t bdl 111t ck 17 last data-in to new read/write command t cdl 111t ck 17 lastdata-into precharge command t rdl 222t ck 16, 21 loadmoderegister command to active or refresh command t mrd 222t ck 26 data-out to high-impedance from precharge command cl = 3 t roh(3) 333t ck 17 cl = 2 t roh(2) 222t ck 17
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3dg7267v-d2 january 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v cc , v ccq = +3.3v; t a = 25c; pin under test biased at 1.4v; f = 1 mhz. 3. i dd is dependent on output loading and cycle rates. speci? ed values are obtained with mini-mum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum speci? cations are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v cc and v ccq must be powered up simultaneously. v ss and v ssq must be at same potential.) the two auto refresh command wake-ups should be repeated any time the tref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate speci? cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a mono-tonic manner. 9. outputs measured at 1.5v with equivalent load: q 50pf 10. t hz de? nes the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = 0v and v ih = 3v with timing referenced to 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v ih (min) and no longer at the 1.5v crossover point. 12. other input signals are allowed to transition no more than once every two clocks and are other-wise at valid v ih or v il levels. 13. i dd speci? cations are tested after the device is properly initialized. 14. timing actually speci? ed by t cks ; clock(s) speci? ed as a reference only at minimum cycle rate. 15. timing actually speci? ed by t wr plus t rp ; clock(s) speci? ed as a reference only at minimum cycle rate. 16. timing actually speci? ed by t wr . 17. required clocks are speci? ed by jedec functionality and are not dependent on any timing parameter. 18. the i dd current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. address transitions average one transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 10ns for 10, and t ck = 7.5ns for 7 and 7.5. 22. v ih overshoot: v ih (max) = v ccq + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il under-shoot: v il (min) = -2v for a pulse width 3ns. 23. the clock frequency must remain constant (stable clock is de? ned as a signal cycling within timing constraints speci? ed for the clock pin) during access or precharge states (read, write, including t wr , and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget (t rp ) begins 7ns for 7; 7.5ns for 7.5 and 7.5ns for 10 after the ? rst clock delay, after the last write is executed. may not exceed limit set for precharge mode. 25. precharge mode only. 26. jedec and pc133, pc100 specify three clocks. 27. t ac for 7/7.5 at cl = 3 with no load is 4.6ns and is guaranteed by design. 28. parameter guaranteed by design.
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3dg7267v-d2 january 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary ordering information part number speed cas latency height* w3dg7267v10d2 100mhz cl=2 30.48 (1.20") W3DG7267V7D2 133mhz cl-2 30.48 (1.20") w3dg7267v75d2 133mhz cl=3 30.48 (1.20") notes: ? consult factory for availability of lead-free products. (f = lead-free, g = rohs compliant) ? product speci? c part numbers are available for source control if needed, please consult factory for the correct part numbe r if a speci? c component vendor is preferred. ? consult factory for availability of industrial temperature (-40c to 85c) option * all dimensions are in millimeters and (inches) package dimensions 17.78 (0.700) 30.48 (1.20) max. 24.49 (0.964) 1.98 (0.078) (2x) 6.35 (0.250) 36.83 (1.450) 42.19 (1.661) 3.18 (0.125) 54.61 (2.150) 1.27 (0.050) typ. 1.27 0.10 (0.050 0039) 8.88 (0.350) 11.43 (0.450) 3.99 (0.157) (2x) 3.81 (0.150) 3.99 (0.157) 133.48 (5.255) max.
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3dg7267v-d2 january 2005 rev. 1 white electronic designs corp. reserves the right to change products or speci? cations without notice. preliminary document title 512mb C 2x32mx72, sdram unbuffered revision history rev # history release date status rev a created datasheet 11-7-01 advanced rev b add "part number" to order info table 1-17-02 advanced rev 0 0.1 updated cap & idd spec 0.2 added package dimentions in millimeters 0.3 removed "ed" from part number 0.4 changed from advanced to preliminary 6-9-04 preliminary rev 1 1.0 added lead-free and rohs notes 1.1 added source control notes 1.2 added industrial temperature options 1.3 added ac specs 1-17-05 preliminary
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